Method of clock rate matching plesiochronous signals

Details Method of clock rate matching plesiochronous signals Method of clock rate matching plesiochronous signals

H - Electricity

04

J

363/17

H04J 3/02 (2006.01) H04J 3/07 (2006.01)

Patent

CA 1157592

ABSTRACT A method of clock rate matching a digitalised analogue signal to a data flow having a pulse frame structure which includes channels (ZKO to ZK31) for the data (Kl to K31)and additional transmission capacity for signals (UR-Sy, Zl to Z17) other than data., the digitalised analogue signal (TnO to Tn31) and data flow having mutually plesiochronous clock rates, said method including the steps of inserting the digital bits of the digitalised analogue signal (TnO to Tn31) into respective bit time slots of a plurality of consecutive channels of each pulse frame, inserting into vacant bit time slots of the additional transmission capacity (ZK16) a clock rate matching signal (++,--) indicating whether the clock rates are effectively synchronous within predetermined limits or have a positive (++,++) or negative (--,--) deviation relative to each other outside said limits, and a reference bit position difference signal (B) indicative of the number of bits in-a pre- determined portion (ZKl) of the channels (ZKl to ZK3) in each pulse frame occupied by the digitalised analogue signal, adjusting, when said deviation is outside said limits, the number of bits (B) in said predetermined channel portion (ZKl) such that said-clock rate matching signa1 (++,--) will again indicate effectively synchronous clock rates, and, where necessary inserting into a vacant portion (R2,ZK16) of said additional transmission capacity, a portion (X) of the digit- alised analogue signal omitted from said predetermined channel portion (ZKl) as a result of said adjustment.

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