Method of clock rate matching plesiochronuous signals

Details Method of clock rate matching plesiochronuous signals Method of clock rate matching plesiochronuous signals

H - Electricity

04

J

363/13

H04J 3/06 (2006.01) H04J 3/07 (2006.01)

Patent

CA 1160773

ABSTRACT A method of clock rate matching a digitalised analogue signal (Tn0 to Tn31) to a data flow having a pulse frame structure which includes channels (ZK0 to ZK31) for the data and additional transmission capacity for signals (UR-Sy, Z1 to Z31) other than data, the digitalised analogue signal (Tn0 to Tn31) and data flow having mutually plesiochronous clock rates, said method including the steps of inserting digital bits forming words of the digitalised analogue signal (Tn0 to Tn31) into respective bit time slots of a plurality of consecutive channels (ZK1 to ZK3, ZK17 to ZK19) of each pulse frame, inserting into vacant bit time slots of the additional transmission capacity (ZK16) a clock rate matching signal (++,--) indicating whether the clock rates are effectively synchronous within predetermined limits or have a positive (++/++) or negative (--,--) deviation relative to each other outside said limits, adjusting, when said deviation is outside said limits, the distribution of words (Tn0 to Tn31) of the digitalised analogue signal in said plurality of consecutive channels (ZK1 to ZK3, ZR17 to ZK19) such that said clock rate matching signal (++,--) will again indicate effectively synchronous clock rates, said synchronism being indicated by the occurrence of alternate positive (++) and negative (--) deviation indicating clock rate matching signals, said positive deviation being indicated by consecutive occurrences of positive deviation indicating clock rate matching signals (++,++), and said negative deviation being indicated by consecutive occurrences of negative deviation indicating clock rate matching signals (--,--).

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