Method of combining gate array and standard cell circuits on...

Details Method of combining gate array and standard cell circuits on... Method of combining gate array and standard cell circuits on...

H - Electricity

01

L

328/127, 356/30

H01L 27/04 (2006.01) H01L 27/02 (2006.01) H01L 27/118 (2006.01)

Patent

CA 1290076

ABSTRACT A Method Of Combining Gate Array and Standard Cell Circuits On A Common Semiconductor Chip A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time. BU9-87-002

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