Method of design analysis of existing integrated circuits

Details Method of design analysis of existing integrated circuits Method of design analysis of existing integrated circuits

G - Physics

06

F

G06F 17/50 (2006.01) G06T 7/00 (2006.01)

Patent

CA 2517651

The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is trade on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

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