H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 21/301 (2006.01) H01L 21/78 (2006.01)
Patent
CA 2345739
A semiconductor wafer covered with protective hard film over the surface is diced into a plurality of chips in such a manner that the protective film does not separate. Two parallel grooves are formed in dicing areas around chips on a GaAs wafer by etching. SiO2 film is deposited as surface protective film over the surface of the semiconductor wafer. As a result, the protective film bends on the border of the groove in the surface of the wafer. The wafer is diced between the two grooves with a blade, and the stresses on the protection film by the edge of the dicing blade concentrate on the bend, resulting in cracks along the bend.
Une plaquette de semi-conducteur recouverte d'une couche mince dure protectrice sur la surface est découpée en une pluralité de puces de manière que la couche mince protectrice ne se sépare pas. Deux rainures parallèles sont formées dans des zones de découpage autour de puces sur une plaquette AsGa par gravure. Une couche mince SiO¿2? est déposée en tant que couche mince de surface protectrice sur la surface de la plaquette de semi-conducteur. Ainsi, une couche mince protectrice plie sur le bord de la rainure dans la surface de la plaquette. La plaquette est découpée entre les deux rainures à l'aide d'une lame, et les contraintes sur la couche mince de protection dues au tranchant de la lame de découpage se concentrent sur la courbure, ce qui a pour résultat la formation de fissures le long de la courbure.
Arima Takahisa
Kusuda Yukihisa
Nippon Sheet Glass Co. Ltd.
Smart & Biggar
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