Method of fabricating a junction field effect transistor

Details Method of fabricating a junction field effect transistor Method of fabricating a junction field effect transistor

H - Electricity

01

L

356/149

H01L 21/265 (2006.01) H01L 21/337 (2006.01) H01L 29/772 (2006.01) H01L 29/808 (2006.01)

Patent

CA 1269764

METHOD OF FABRICATING A JUNCTION FIELD EFFECT TRANSISTOR ABSTRACT Method of fabricating a junction field effect transistor, specifically a static induction transistor, which may be of GaAs. Elongated N-type source regions are formed in an N-type epitaxial layer of semiconductor material grown on a substrate. A tri-level mask is formed having elongated openings exposing portions o the epitaxial layer intermediate between the source regions. The openings are wider at the bottom than at the top. P-type gate regions are formed by ion-implanting P-type doping material through the mask openings. Silicon dioxide is deposited through the openings by angle evaporation to form generally trapezoidal-shaped temporary gate members over the gate regions. The tri-level mask is removed, a layer of silicon nitride is deposited, and a layer of masking material is deposited. Some of the masking material is removed; then the temporary gate members and silicon nitride immediately adjacent thereto are removed. Metal for making ohmic contact to the P-type gate regions is deposited through the resulting openings. The remaining masking material is removed, openings are formed in the silicon nitride over the N-type source regions, and metal for making ohmic contact to the N-type source regions is deposited in the openings.

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