Method of fabricating a self-aligned metal- semiconductor fet

Details Method of fabricating a self-aligned metal- semiconductor fet Method of fabricating a self-aligned metal- semiconductor fet

H - Electricity

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H01L 21/20 (2006.01) H01L 29/08 (2006.01) H01L 29/80 (2006.01) H01L 29/812 (2006.01)

Patent

CA 1266812

A B S T R A C T Method of Fabricating a Self-Aligned Metal-Semiconductor FET A method for the fabrication of self-aligned MESFET structures (30) with a recessed refractory submicron gate. After channel formation (32) on a SI substrate (31), which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing the refractory gate (33G) is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of e.g. GaAs using MOCVD or MBE processes resulting in poly-cry- stalline material over the gate "mask" and in mono-cry- stalline material (34S, 34D) on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes (35S, 35D). In order to further improve process reliability, insulat- ing sidewalls (43-43) can be provided at the vertical edges of the gate (33G) to avoid source-gate and drain- gate shorts.

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