H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/126
H01L 21/027 (2006.01) H01L 21/22 (2006.01) H01L 21/28 (2006.01) H01L 21/336 (2006.01)
Patent
CA 2002885
ABSTRACT A method is disclosed for fabricating submicron silicon gate metal-oxide-semiconductor field effect transistors (MOSFETs) which have threshold and punchthrough implants that are self-aligned to the gate electrode and source and drain regions. A layer of dielectric material is either deposited or grown on the surface of a substrate, and a trench, which defines the region of the MOSFET gate electrode, is formed in the dielectric layer. A gate oxide is formed at the exposed substrate at the bottom of the trench, and an implant is performed into the silicon substrate wherever there is gate oxide, but not into the portion of the substrate covered by the original dielectric layer. A layer of polysilicon, preferably doped, or another metallic film is then deposited onto the surface. The polysilicon is etched back to the top surface of the dielectric layer, thereby leaving polysilicon in the trench to form the gate electrode. The dielectric layer is then etched back preferentially to a thickness approximately equal to the thickness of the gate dielectric, and a high-dose implant is performed through the reduced thickness dielectric layer into the silicon substrate, except for the areas covered by the polysilicon gate to form the source and drain regions of the MOSFET.
Berg John E.
Smart & Biggar
Standard Microsystems Corporation
LandOfFree
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