H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149
H01L 29/80 (2006.01) H01L 21/28 (2006.01) H01L 21/31 (2006.01)
Patent
CA 1184672
ABSTRACT OF THE DISCLOSURE A field effect transistor fabricating method comprises forming a surface portion of a semiconductor sub- strate with an impurity region for a channel; forming a first material layer having a width substantially equal to that of a gate electrode in such a position on the semiconductor sub- strate as is to be formed with the gate electrode, a second material layer having a width larger than that of the first material layer above the first material layer and source and drain regions by ion implantation using the first and second material layers thus formed as a mask. The source and drain electrodes are formed in contact with the source and drain regions. A third material layer that has a selectivity with the first material layer in its etching characteristics is formed on the semiconductor body thus far prepared. An aperture is formed by removing the first material layer using the third material layer as a mask. The gate electrode is then formed in the aperture. The resulting transistor has the advantages of being more planar and having a shorter gap between the source and drain regions while keeping the channel length short. The increased transconductance between source and drain increases the speed of operation.
420517
Nakamura Michiharu
Takahashi Susumu
Ueyanagi Kiichi
Umemoto Yasunari
Hitachi Ltd.
Kirby Eades Gale Baker
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