Method of fabricating highly lattice mismatched quantum well...

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H01L 21/36 (2006.01) H01L 21/20 (2006.01) H01L 29/02 (2006.01) H01S 5/34 (2006.01)

Patent

CA 2026086

A METHOD OF FABRICATING HIGHLY LATTICE MISMATCHED QUANTUM WELL STRUCTURES ABSTRACT A method of fabricating a semiconductor heterostructure includes the growth of a quantum well active region that is highly lattice-mismatched relative to a substrate. A buffer layer having a thickness above a critical value is grown on the substrate whereby the stress due to a lattice constant mismatch between the buffer layer and substrate is relieved through the formation of misfit dislocations. A strained superlattice structure is grown on the buffer layer in order to terminate any upwardly-propagating dislocations, An unstrained barrier layer is subsequently grown on the superlattice structure. The fabrication method concludes with the growth of a quantum well structure on the unstrained layer wherein a lattice constant mismatch between the quantum well structure and the unstrained barrier layer is smaller than the lattice constant mismatch between the quantum well structure and the substrate. As a result, only a fraction of the stress due to the large lattice mismatch between the quantum well structure and the substrate is accommodated by coherent strain in the quantum well structure, while the remainder of the stress is relieved through the formation of misfit dislocations spatially separated from the quantum well structure.

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