Method of fabricating interconnect layers on an integrated...

Details Method of fabricating interconnect layers on an integrated... Method of fabricating interconnect layers on an integrated...

H - Electricity

01

L

356/134, 117/64

H01L 21/285 (2006.01) H01L 21/60 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1269285

A METHOD OF FABRICATING INTERCONNECT LAYERS ON AN INTEGRATED CIRCUIT CHIP USING SEED-GROWN CONDUCTORS ABSTRACT OF THE DISCLOSURE A process of forming an interconnection layer for an integrated circuit in which the conductor pattern is embedded in a layer of insulating material to form a conductor-insulator layer. The conductor-insulator layer is formed by selectively filling recesses in a layer of insulating material with conductive material. The filling of the recesses is accomplished in two steps: depositing an initial layer of conductive material by a process which selectively deposits the conductive material on a seed material located in the bottom of the recesses, then depositing the bulk of the conductive material by a process which selectively deposits conductive material on existing conductive material.

543114

Affiliated with

Also associated with

Rating

Method of fabricating interconnect layers on an integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating interconnect layers on an integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating interconnect layers on an integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1216682