Method of fabricating self-aligned lateral bipolar transistor

Details Method of fabricating self-aligned lateral bipolar transistor Method of fabricating self-aligned lateral bipolar transistor

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H01L 21/265 (2006.01) H01L 21/033 (2006.01) H01L 21/20 (2006.01) H01L 21/3215 (2006.01) H01L 21/8222 (2006.01) H01L 29/735 (2006.01)

Patent

CA 1153129

ABSTRACT OF THE DISCLOSURE A surface oriented lateral bipolar transistor having a base of narrow width is fabricated by using a doped polycrystalline silicon layer as an ion implantation mask when implanting ions for the emitter and base regions. In forming the doped polysilicon mask, a first layer of dopant masking material is formed on the surface of a semiconductor substrate, a second layer of un- doped polysilicon is formed over the first layer, and a third layer of dopant masking material is formed over the second layer. Portions of the second and third layers are removed and a dopant is diffused into the exposed edge portion of the second layer. The third layer and the undoped portion of the second layer are then removed thereby leaving only the doped portion of the second layer on the first layer.

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