H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/132
H01L 21/428 (2006.01) H01L 21/268 (2006.01) H01L 21/3213 (2006.01) H01L 21/336 (2006.01)
Patent
CA 1161969
METHOD OF FABRICATING SEMICONDUCTOR DEVICES USING LASER ANNEALING Abstract of the Disclosure In the manufacture of VLSI (very large scale integrated) MOS (metal-oxide-semiconductor) circuits, a polysilicon gate is deposited on an oxide layer overlaying a silicon substrate. Ideally, the polysilicon gate is made extremely small and with sharply defined vertical boundaries. The invention proposes depositing a polysilicon layer, covering a region of the layer with an antireflective coating, and laser annealing the layer. Laser radiation is absorbed to a higher level by the coated region than elsewhere and consequently the polysilicon layer in this region melts and recrystallizes into large grains. The polysilicon layer is then etched using etch conditions ensuring preferential etching of unrecrystallized polysilicon in comparison with recrystallized polysilicon. Consequently, except at the coated region, the polysilicon is etched quickly and there is very little undercutting of the gate region. Preferential etching methods based on differing dopant levels in polysilicon are known but do not produce the sharp edge definition enabled using the present process. - i -
402487
Calder Iain D.
Naem Abdalla A.h.
Naguib Hussein M.
Nortel Networks Limited
Wilkinson Stuart
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