Method of forming a compact multi-level interconnection...

Details Method of forming a compact multi-level interconnection... Method of forming a compact multi-level interconnection...

H - Electricity

05

K

356/134, 356/136

H05K 1/11 (2006.01) H01L 21/768 (2006.01) H01L 23/522 (2006.01)

Patent

CA 1089112

METHOD OF FORMING A COMPACT MULTI-LEVEL INTERCONNECTION METALLURGY SYSTEM FOR SEMICONDUCTOR DEVICES Abstract of the Disclosure In this method, the multi-level interconnection metallurgy system is made more compact by eliminating the need for pads normally associated with via connections between the metallurgy layers. The method consists of forming a first dielectric layer on a semiconductor substrate, forming the first interconnection metallurgy level on the first layer, depositing a second dielectric layer over the metallurgy layer wherein the second dielectric layer is a material different from the material of the first dielectric layer, forming via holes in the second dielectric layer of a diameter substantially equal to or larger than the width of the underlying interconnection lines of the first metallurgy pattern, and forming a second interconnection metallurgy system over the second dielectric layer with the conductive lines of the second metallurgy layer having a uniform width over the via holes.

180181

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