Method of forming plunar isolation regions having field...

Details Method of forming plunar isolation regions having field... Method of forming plunar isolation regions having field...

H - Electricity

01

L

356/163

H01L 21/42 (2006.01) H01L 21/265 (2006.01) H01L 21/762 (2006.01) H01L 29/06 (2006.01)

Patent

CA 1191280

ABSTRACT OF THE DISCLOSURE A method for manufacturing integrated circuit devices wherein semiconductor elements are isolated by insulation mate- rial comprising the following steps of: a) providing a mask pat- tern on a predetermined semiconductor element region of a semi- conductor substrate; b) introducing by first ion-implantation impurities of the same conductivity type as that of the substrate into the substrate using the mask pattern as an ion-implantation mask; c) etching the substrate and forming a groove using the mask pattern as an etching mask in a manner that part of the impurities remain at least under the mask pattern in the side walls of the groove; d) introducing by second ion-implantation impurities of the same conductivity type as that of the substrate through the groove into the substrate; e) burying insulation material in the groove; and f) forming a semiconductor element on the predetermined semiconductor element region.

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