Method of forming power semiconductor devices with...

Details Method of forming power semiconductor devices with... Method of forming power semiconductor devices with...

H - Electricity

01

L

H01L 21/22 (2006.01) H01L 21/20 (2006.01) H01L 21/331 (2006.01) H01L 29/739 (2006.01)

Patent

CA 2213840

A method of manufacturing a semiconductor device and device in which a sacrificial N shelf layer is grown on a P+ semiconductor substrate to contain the out-diffusion of dopant from the substrate. An N + buffer layer is grown on the N shelf layer and an N- epitaxial layer is grown on the N + buffer layer. The presence of the N shelf layer, which is consumed by the substrate dopant during further device fabrication, allows the integrated dopant level of the N + buffer layer to be accurately controlled in the finished device.

Une méthode de fabrication de dispositifs à semi-conducteurs et de dispositifs dans lesquels une couche intermédiaire N sacrificielle est créée sur un substrat semi-conducteur P+ pour absorber la diffusion du dopant à l'extérieur du substrat. Une couche tampon N + est créée sur la couche intermédiaire N et une couche épitaxiale N- est créée sur la couche tampon N +. La présence de la couche intermédiaire N, qui est éliminée par le dopant du substrat pendant que se poursuit la fabrication du dispositif, permet de contrôler avec précision la concentration de dopant intégrée de la couche tampon N + dans le dispositif fini.

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