Method of generating addresses to a paged memory

Details Method of generating addresses to a paged memory Method of generating addresses to a paged memory

G - Physics

06

F

354/239

G06F 12/02 (2006.01)

Patent

CA 1066813

METHOD OF GENERATING ADDRESSES TO A PAGED MEMORY Abstract of the Disclosure An input-output processing system which performs communication and control functions in a larger data processing system includes a processor for address development to paged memory and program instruction execution for I/O command sequences. In generating memory addresses, instructions are provided an address syllable which references a processor register as an index and a displacement. The contents of the register and the displacement define a memory effective address. A scratchpad memory is provided for storing page table words in levels corresponding to priority levels of processes, and stored page table words are accessed according to the least significant bits of the page number of the effective address. A page base address is taken from an accessed page table word and is concatenated with the effective address to define an absolute memory address. - 1 -

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