H - Electricity – 01 – L
Patent
H - Electricity
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H01L 21/324 (2006.01) H01L 21/314 (2006.01) H01L 21/316 (2006.01) H01L 21/318 (2006.01) H01L 21/3205 (2006.01) H01L 21/322 (2006.01) H01L 29/04 (2006.01)
Patent
CA 1079863
METHOD OF GETTERING USING BACKSIDE POLYCRYSTALLINE SILICON Abstract An integrated circuit structure and method for manu- facturing same which provides for gettering with a back- side layer of polycrystalline silicon. The gettering of unwanted impurities from the integrated circuits involves the deposition of a polycrystalline silicon film on a semi- conductor wafer prior to any or some high temperature pro- cessing steps. The semiconductor body is then subjected to the normal semiconductor processing steps to form semi- conductor devices on the surface opposite to the surface having the polycrystalline silicon layer. During these high temperature processing steps, unwanted impurities such as copper, iron, nickel, sodium and potassium ions move toward and into the polycrystalline silicon layer and thereby away from the semiconductor devices. This produces improved yield in the integrated circuit process.
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