Method of making a large scale integrated device having a...

H - Electricity – 05 – K

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356/132, 96/249,

H05K 3/06 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1088382

Abstract of the Disclosure A method of surface planarizing large scale integrated devices, including a double metal lift-off step is described. A first resist layer is deposited on an insulating layer which is formed over a first metal layer with a pattern structure. The resist layer is then masked by another metal layer. Then, a second resist layer is deposited over the metal masking, and is exposed and developed to delineate via holes therein. The metal masking, first resist layer and insulating layer are successively etched to define the via holes. During this procedure the second esist layer is automatically removed. A second metal layer is then deposited on the metal masking layer and in the defined via holes. The first resist layer is then lifted off which in turn accomplishes the double metal lift-off of the metal masking and the second metal layer. Subsequently, a third conductive metal pattern layer may, if desired, be deposited over the insulating layer and the metal filled via holes therein. A third resist layer is then deposited on the third metal layer and is exposed and develop- ed to delineate a conductive pattern on the resist layer. The third resist layer is then exposed and developed and then the conductive pattern is formed on the planar surface of the device by lift-off reactive ion etching or other convention- al techniques. - 1 -

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