Method of making a semiconductor device comprising...

H - Electricity – 01 – L

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H01L 21/60 (2006.01) H01L 21/00 (2006.01) H01L 21/033 (2006.01)

Patent

CA 1298000

20104-8257 ABSTRACT A method of manufacturing an integrated circuit comprising a field effect transistor having an insulated gate (35) and a further circuit element having a first (9) and a second electrode zone (14) of opposite conductivity types. Simultaneously with the gate (35) a conductive pattern (11) separated by an insulating layer (34) from the first electrode zone (9) is provided on the first electrode zone (9). This pattern (11) or a part of this pattern is used to define the edge or part of the edge of the doping opening (12) for the second electrode zone (14). A second insulating layer (16) is provided on the pattern (11) and is removed locally by anisotropic etching in such a manner that in the doping opening (12) edge portions (17) (16) are left. Subsequently, a conductive layer (22) for connection of the second electrode zone (14) is provided, which extends over the second insulating layer (16), over the pattern (11) and over the edge portions (17) (16) into the opening (12) of reduced size and on the second electrode zone (14). The contact opening for the second electrode zone (14) can thus be derived without alignment tolerance from the doping opening (12).

532338

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