H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/162
H01L 21/469 (2006.01) G02B 6/02 (2006.01) H01L 21/768 (2006.01) H01L 23/532 (2006.01)
Patent
CA 2006174
ABSTRACT OF THE DISCLOSURE A method of fabricating a semiconductor device is disclosed wherein a first dielectric layer is applied over an interconnect layer having tracks defining a conductive pattern, the first dielectric layer forming valleys between the tracks of the interconnect layer, spin-on glass is applied over said first layer to planarize it by forming spin-on glass zones in the valleys defined by the first dielectric layer, and a second layer is applied to the planarized first layer, whereby the first and second layers and said spin-on glass zones form a composite multi-layer film. The first layer is formed such that it has compressive stress at room temperature to prevent cracking in the composite multi-layer film during subsequent heat treatment. The second layer can be another dielectric layer or a further interconnect layer applied directly to the first layer and SOG planarization layer. The method can also be applied to other fields, such as the manufacture of optical fibers, emission diodes and the like.
Azelmad Abdellah
Ouellet Luc
Marks & Clerk
Mitel Corporation
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