H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/128
H01L 21/00 (2006.01) H01L 21/033 (2006.01) H01L 21/265 (2006.01) H01L 21/285 (2006.01) H01L 21/3105 (2006.01) H01L 21/336 (2006.01) H01L 29/08 (2006.01) H01L 29/78 (2006.01)
Patent
CA 1237537
ABSTRACT OF THE DISCLOSURE A method for the manufacture of a large scale integration (LSI) MOS field effect transistor wherein a gate electrode is generated on a doped silicon substrate, source/drain regions are formed by ion implantation using the gate electrode as an implantation mask and the source/drain regions are shielded by means of an oxide layer extending to the sidewalls of the gate electrode so that the diffusion of the implanted source/drain regions under the gate electrode area are reduced. The specific improvement of the present invention involves applying a readily flowable silicate glass layer as a gate edge masking for the source/drain ion implantation after formation of the gate electrode, the silicate glass layer being applied by deposition from the vapor phase at a thickness such that the dopant ions in the subsequent source/drain ion implantation are still implanted into the zone near the surface under the silicate glass layer but ion implantation into the zones at the edges of the gate is suppressed.
479324
Jacobs Erwin P.
Neppl Franz
Schwabe Ulrich
Aktiengesellschaft Siemens
Fetherstonhaugh & Co.
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