H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149
H01L 21/82 (2006.01) H01L 21/28 (2006.01) H01L 21/31 (2006.01) H01L 21/311 (2006.01) H01L 21/8249 (2006.01) H01L 27/06 (2006.01)
Patent
CA 1296111
A METHOD OF MANUFACTURING A POLYSILICON EMITTER AND A POLYSILICON GATE USING THE SAME ETCH OF POLYSILICON ON A THIN GATE OXIDE ABSTRACT OF THE DISCLOSURE A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrys- talline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is depos- ited on the bipolar and MOS regions of the silicon sub- strate, and the substrate is masked and etched for form- ing the emitter and gates of the bipolar and MOS devices, respectively. F5/10272-40
588500
Brassington Michael P.
El-Diwany Monir H.
Razouk Reda R.
Tuntasood Prateep
Brassington Michael P.
El-Diwany Monir H.
National Semiconductor Corporation
Razouk Reda R.
Smart & Biggar
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