Method of manufacturing a semiconductor device

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H01L 21/28 (2006.01) H01L 21/033 (2006.01) H01L 21/321 (2006.01) H01L 21/768 (2006.01) H01L 21/8238 (2006.01)

Patent

CA 1176761

PHN 9922 11.11.1981 ABSTRACT. Method of manufacturing a semiconductor device. A method of manufacturing an integrated cir- cuit having at least an insulated gate field effect transistor (IGFET). Provided on the silicon surface (2) are successively a gate oxide layer (15) and a doped sili- con layer (16) which are patterned by etching by means of a silicon nitride-containing mask (17) which comprises the gate electrode(s) (16A, B) and interconnections (16C). Nitrogen ions are implanted in the surface parts not under- lying the mask (17). By thermal oxidation only the edges of the silicon pattern (16) are oxidized. By ion implanta- tion the source and drain zones (23, 24, 27, 28) are formed, the gate electrodes serving as an implantation mask. If desired, the threshold voltage may then be adjusted by ion implantation in the channel region via the gate electrode. The invention is of particular importance for the manu- facture of complementary IGFET pairs in which a transistor is provided in a bowl-shaped zone (11) which is bounded by a p-n junction (14) terminating at the surface between a boron-doped p-type (13) and an adjoining phosphorus- doped n-type channel stopper zone (7).

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