Method of manufacturing a semiconductor device and...

Details Method of manufacturing a semiconductor device and... Method of manufacturing a semiconductor device and...

Category

H - Electricity

Subcategory

01

Subsubcategory

L

CPC

356/149

IPC codes

H01L 21/385 (2006.01) H01L 21/22 (2006.01) H01L 21/74 (2006.01) H01L 21/8238 (2006.01) H01L 21/8249 (2006.01)

Type

Patent

Patent number

CA 1216966

Description

12 ABSTRACT: A method of manufacturing a semiconductor device, in which semiconductor circuit elements are provided in regions (6A,7A,11A) formed by diffusion from one or more buried layers (6,7,11) in an epitaxial layer (13). Accord- ing to the invention, the diffusion is carried out in a manner such that a surface layer (13A) having substantially the same doping as the original epitaxial layer (13) is left above the buried layer or layers, which surface layer serves as a reference doping for the insulated gate field effect transistors to be formed. This is of particular important for threshold voltage determination in CMOS circuits having adjoining "twin tub" regions (6A,11A) diffused from buried layers of opposite conductivity types.

Application Number

458184

Affiliated with

Also associated with

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