H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/177
H01L 21/36 (2006.01) H01L 21/3213 (2006.01)
Patent
CA 1243133
ABSTRACT: Method of manufacturing a semiconductor device, in which a double layer - consisting of polycrystalline Si and a silicide - present on a layer of silicon oxide is etched in a plasma. A method of manufacturing a semiconductor device, in which a double layer (12) consisting of a layer of polycrystalline silicon (13) and a top layer of a silicide (14) is applied to a surface (11) of a semiconductor substrate (6) coated with a layer of silicon oxide (10). After an etching mask (15) has been provided, the double layer (12) is etched in a plasma formed in chlorine gas to which up to 20 % by volume of tetrachloromethane is added until the layer of polycrystalline silicon is etched. Thus, the double layer (12) is etched anisotropically and the layer of silicon oxide (10) is attacked in practice to a very small extent.
504192
Van Arendonk Anton P.m.
Van Roosmalen Alfred J.
Koninklijke Philips Electronics N.v.
Van Steinburg C.e.
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