H - Electricity – 01 – L
Patent
H - Electricity
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H01L 21/02 (2006.01) H01L 21/48 (2006.01) H01L 21/50 (2006.01) H01L 21/56 (2006.01) H01L 21/58 (2006.01) H01L 23/31 (2006.01) H01L 23/485 (2006.01) H01L 23/495 (2006.01)
Patent
CA 2159243
In a method of manufacturing a semiconductor device comprising a semiconductor chip and a carrier film which includes an insulating film and wiring patterns formed on one of main surfaces of the insulating film, an adhesive layer is formed on a surface of a semiconductor wafer having a number of integrated circuits. Each of the integrated circuits has electrode pads for external connection on the foregoing surface of the semiconductor wafer. Subsequently, openings are formed at regions of the adhesive layer corresponding to the electrode pads, and then, the integrated circuit is cut from the semiconductor wafer so as to obtain the semiconductor chips. Thereafter, the electrode pads of the semiconductor chip and the wiring patterns of the carrier film are connected to each other through the corresponding openings of the adhesive layer, respectively. Then, the semiconductor chip and the carrier film are bonded together via the adhesive layer interposed therebetween. It may be arranged that the adhesive layer is formed on the carrier film rather than on the semiconductor chip.
Kata Keiichiro
Matsuda Shuichi
G. Ronald Bell & Associates
Nec Electronics Corporation
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