Method of manufacturing flat panel backplanes including...

Details Method of manufacturing flat panel backplanes including... Method of manufacturing flat panel backplanes including...

G - Physics

02

F

G02F 1/01 (2006.01) G02F 1/13 (2006.01) G02F 1/1362 (2006.01) G02F 1/15 (2006.01) H05K 1/16 (2006.01)

Patent

CA 2054935

Flat panel displays are provided with overlying interconnected and hence redundant bus lines to reduce fatal defects. The redundant, generally row lines are interconnected at least at two locations on a line and can be connected at each pixel to further reduce defects. The redundant row or gate line is formed by an overlying light shield line which preferably is of low resistivity and enhances the operation of the displays. The display can include subdivided subpixels and one defective subpixel is generally an acceptable non-fatal display defeat, since the rest of the subpixels are still operative. The subpixels can be formed with common or redundant column bus lines.

Affiliated with

Also associated with

Rating

Method of manufacturing flat panel backplanes including... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing flat panel backplanes including..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing flat panel backplanes including... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1974046