Method of producing a thin silicon-on-insulator layer

Details Method of producing a thin silicon-on-insulator layer Method of producing a thin silicon-on-insulator layer

H - Electricity

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H01L 21/20 (2006.01) G03F 1/14 (2006.01) H01L 21/306 (2006.01) H01L 21/762 (2006.01)

Patent

CA 2066193

2066193 9105366 PCTABS00004 A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy (24) includes properly doping a prime silicon wafer (20) for the desired application, growing a strained Si1-x Gex alloy layer (24) onto seed wafer (20) to serve as an etch stop, growing a silicon layer (26) on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer (20) and a test wafer (30), bonding the oxide surfaces of the test (30) and prime wafers (20), machining the backside of the prime wafer (20) and selectively etching the same to remove the silicon (20 and 22) removing the strained alloy layer (24) by a non-selective etch, thereby leaving the device region silicon layer (26). In an alternate embodiment, the process includes implanting germanium, tin, or lead ions to form the strained etch stop layer (24).

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