H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149
H01L 21/336 (2006.01) H01L 21/225 (2006.01) H01L 21/8238 (2006.01) H01L 27/092 (2006.01)
Patent
CA 2031636
ABSTRACT OF THE DISCLOSURE The method of producing a CMOS transistor device. A pair of device regions are formed and separated relation from each other by a field oxide film on a pair of corresponding well regions formed in a semiconductor substrate. A gate insulating film and a gate electrode are sequentially formed on each of the device regions. The gate insulating film is removed through a mask of the patterned gate electrode to expose a silicon active surface at least in one of the device regions. A diborane gas containing P type boron impurity is applied to the silicon active surface to form thereon a boron adsorption film. N type arsenic impurity is doped into the other device region by ion implantation to form N type source and drain regions while masking the one device region. The boron is diffused from the adsorption film into the one device region to form P type source and drain regions by annealing of the substrate.
Aoki Kenji
Saito Naoto
Aoki Kenji
Borden Ladner Gervais Llp
Saito Naoto
Seiko Instruments Inc.
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