Method of programming a multi-level memory device

G - Physics – 11 – C

Patent

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Details

G11C 16/10 (2006.01) G11C 11/34 (2006.01) G11C 11/56 (2006.01) G11C 16/12 (2006.01)

Patent

CA 2491228

A method (Fig. 1) of programming a multi-level memory chip in which the first, or lowest, voltage memory state (11) through the next-to-last voltage memory state (01) are programmed by a plurality of programming pulses (P; 40-47) increasing incrementally in voltage (30), alternated with a plurality of verify pulses (V; 50-57), and in which the last, or highest, voltage memory state (00) of the memory cell is programmed with a programming pulse (60) of the threshold voltage required for charging the memory cell to the highest voltage memory state. The programming method provides accuracy in programming the intermediate memory states (10, 01) of the cell, while providing speed in programming the last memory state (00) of the cell to increase the overall speed of the program~ming the memory cell.

L'invention concerne un procédé de programmation d'une puce mémoire à niveaux multiples dans laquelle le premier état (11) de mémoire de tension, ou le plus bas, jusqu'à l'avant dernier état de mémoire de tension (01) sont programmés par plusieurs impulsions de programmation (P; 40-47) augmentant progressivement en tension (30) en alternance avec plusieurs impulsions de vérification (V; 50-57), et dans laquelle le dernier état de mémoire de tension (00), ou le plus élevé, de la cellule de mémoire est programmé avec une impulsion de programmation (60) de la tension seuil requise pour charger ladite cellule à l'état de mémoire de tension le plus élevé. Le procédé de programmation offre la précision au niveau de la programmation des états de mémoire intermédiaires (10, 01) de la cellule, mais aussi la vitesse de programmation du dernier état de mémoire (00) de la cellule pour accroître la vitesse générale de programmation de la cellule de mémoire.

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