Method of propagation delay testing a level sensitive...

Details Method of propagation delay testing a level sensitive... Method of propagation delay testing a level sensitive...

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G06F 11/00 (2006.01) G01R 31/28 (2006.01) G01R 31/317 (2006.01) G01R 31/3185 (2006.01) G06F 1/10 (2006.01) G06F 7/00 (2006.01) G06F 7/57 (2006.01) G11C 19/00 (2006.01) H03K 3/037 (2006.01) H03K 19/08 (2006.01) H03K 19/20 (2006.01)

Patent

CA 1075770

METHOD OF PROPAGATION DELAY TESTING A LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM ABSTRACT Propagation delay testing is perfomed on a generalized and modular logic system that contains embedded arrays and can be used as arithmetic/logical/control unit in a digital computer or data processing system. Each such unit can be composed of combinatorial logic and storage circuitry. The storage circuitry may be of two types, randomly arranged latches, or arrays of storage cells. In the organization presented here the latches are arranged such that they have the capability of perform- ing scan-in/scan-out operations independently of system control. Using this scan capability, the method of the invention provides for the state of the storage latches to be preconditioned and independent of prior circuit history. Selected propagation paths are sensitized by patterns from an automated test generator or designer supplied patterns. By alternating selected inputs and by applying proper timing control, propagation delay indications through the selected paths are obtained to determine delay behavior of the logic system. The above ABSTRACT is not to be taken either as a complete exposition or as a limitation of the present invention, the full nature and extent of the invention being discernible only by reference to and from the entire disclosure. FI 9-76-017 -1-

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