Method of synchronizing a quadphase receiver and a clock...

H - Electricity – 04 – L

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340/205

H04L 7/02 (2006.01) H04L 7/027 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1154514

15.5.79 1 PHN.9387 ABSTRACT "Method of synchronizing a quadphase receiver and clock synchronization device for carrying out the method" The invention relates to a method for the clock synchronization of a receiver for demodulating a quadphase coded data signal and to a clock synchroniza- tion device for carrying out the method. Four elementary signal forms can be distinguished in a quadphase coded data signal. Each ele- mentary signal form represents two-bit information, these two bits being transmitted in a first and a second half bit interval and these two bits being transmitted in the inverted form in a third and a fourth half bit interval. The information in the second interval is consequently highly correlated with the information in the first bit interval. The four quadphase code words have been chosen from the sixteen code words which can be formed with four bits and that in such a manner that only two-bit information is transmitted with these four bits. This is achieved by making the first and the second bit of the quadphase code word equal to the two-bit information of the signal to be coded and by making the third and the fourth bit equal to the inverse value of the two-bit information. In the method according to the invention the first bit is compared (correlated) with the third bit and the second bit with the fourth bit: a high degree of correlation indicates 15.5.79 2 PHN.9387 that synchronization has been obtained and a low degree indicates absence of synchronization. The invention is used in the field of optical and magnetic recording and in the field of data transmission over physical pairs of wires.

347977

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