Method of testing an integrated circuit

Details Method of testing an integrated circuit Method of testing an integrated circuit

G - Physics

01

R

324/58.1

G01R 31/28 (2006.01) G01R 31/317 (2006.01)

Patent

CA 1164947

PHF 79050 10 19.3.80 ABSTRACT: Method of testing an integrated circuit. In order to set the circuit to be tested to a test mode, at least one output is led out via an output stage, and the input and output of said output stage in- ternally leads to an exclusive-OR gate. As long as the output has a comparatively high ohmic termination, as is the case during the normal mode of operation, the ex- clusive-OR gate will carry the same signal for both sig- nal conditions of the output. For the purpose of testing a complementary pulse pattern is applied to the output, so that the exclusive OR gate supplies an opposite sig- nal, which establishes the test mode. The output of the exclusive-OR gate may lead to a bistable multivibrator, so that for establishing the test mode only a single complementary signal is required.

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