Method of testing embedded memory array and embedded memory...

Details Method of testing embedded memory array and embedded memory... Method of testing embedded memory array and embedded memory...

G - Physics

06

F

G06F 11/00 (2006.01) G11C 29/26 (2006.01)

Patent

CA 2345605

A memory test controller comprises a test instruction register array for storing a plurality of test instructions, each register having instruction fields for storing instruction data specifying operations to be performed on the memory array, a repeat module for repeating a group of one or more of the test instructions with modified data, the repeat module including storage means for storing instruction field modification data; and each register of the test instruction register array including an instruction field for enabling or disabling the repeat module.

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