Method to control error floor in analog neural ldpc decoder

Details Method to control error floor in analog neural ldpc decoder Method to control error floor in analog neural ldpc decoder

H - Electricity

03

M

H03M 13/11 (2006.01) G06N 3/02 (2006.01) H03M 13/19 (2006.01)

Patent

CA 2651256

Analog decoder for (16,4) Hamming code is simulated with neural design of the check nodes. Error distributions of 3D and 4D mapping for various check nodes based on multilayer perceptron architecture is obtained in simulation after supervised training of neural mappers. For random code-words performance of neural decoder is found to be suboptimal to atanh(.) based ideal decoder. Error floor is shown to be a function of the error distribution in the check nodes. Optimal distribution is achieved when error for training points and those most remote from training points are close to one another with overall precision been about twice better. Control of the error floor via optimization of the error distribution in the check node's mappers is demonstrated, improving the achieved error floor for neural analog type decoder down to BER values of about 10 -6. Over-enhanced error distribution (with precision for intermediate points higher than that for training ones) exhibit deterioration in the performance, demonstrating error floor of about 10 -4 BER.

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