Methods and apparatus for semiconductor testing

H - Electricity – 01 – L

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H01L 21/66 (2006.01) G01R 31/26 (2006.01) G05B 23/02 (2006.01) G06F 17/00 (2006.01)

Patent

CA 2448460

A method and apparatus for testing semiconductors according to various aspects of the present invention comprises a test system comprising an outline identification element configured to identify significant data in a set of test results. The test system may be configured to provide the data in an output report. The outlier identification element suitably performs the analysis at run time. The outlier identification element may also operate in conjunction with a smoothing system to smooth the data and identify trends and departments from test result norms.

L'invention porte sur un procédé et un testeur de semi-conducteurs selon différentes variantes de cette invention qui comprend un système de test dont un élément d'identification d'une valeur aberrante est configuré pour identifier des données importantes dans un ensemble de résultats du test. Le système de test peut être configuré pour générer les données dans un rapport d'émission. L'élément d'identification de valeur aberrante effectue de manière appropriée l'analyse pendant la durée d'exécution et peut également fonctionner conjointement avec un système de lissage permettant de lisser les données et d'identifier des tendances et des écarts découlant des normes de résultats du test.

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