Methods and apparatus to compute crc for multiple code...

Details Methods and apparatus to compute crc for multiple code... Methods and apparatus to compute crc for multiple code...

H - Electricity

03

M

H03M 13/09 (2006.01) H03M 13/00 (2006.01)

Patent

CA 2692719

A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. A transport block CRC is calculated for a transport block including a plurality of information bit. A transport block including the transport block CRC is segmented into a plurality of subsets and a plurality of cyclic redundancy checks are calculated for the plurality of subsets. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information bits. In addition, a transport block cyclic redundancy check may be calculated based on all the information bits.

La présente invention concerne un procédé et un circuit pour générer des vérifications de redondance cyclique. Le procédé calcule une pluralité de vérifications de redondance cyclique pour un bloc de transport avec une pluralité de bits d'information. Un CRC de bloc de transport est calculé pour un bloc de transport comprenant une pluralité de bits d'information. Un bloc de transport comprenant le CRC du bloc de transport est segmenté en une pluralité de sous-ensembles et une pluralité de vérifications de redondance cyclique est calculée pour la pluralité de sous-ensembles. Au moins une vérification de redondance cyclique, parmi la pluralité, est calculée en fonction d'un sous-ensemble de bits d'informations. En outre, une vérification de redondance cyclique de bloc de transport peut être calculée en fonction de tous les bits d'information.

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