Microcode addressing technique for controlling memory search

Details Microcode addressing technique for controlling memory search Microcode addressing technique for controlling memory search

G - Physics

06

F

354/230.73

G06F 9/32 (2006.01) G06F 9/26 (2006.01)

Patent

CA 1141038

Abstract of the Disclosure A microcode addressing system is shown which has two modes of opera- tion for different memory search functions. The first mode, the Slow mode in which the memory operates at a standard read rate, is the mode in which the computer central processing unit performs predetermined sequential tasks in a normal fashion. The second mode of operation is the Fast mode of operation in which the memory responds to unpredetermined, dynamically changing events in the computer system at a faster than standard cycle time in order to search for and identify a particular word in central memory.

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