Microcode instruction sequencing in pipeline processors

Details Microcode instruction sequencing in pipeline processors Microcode instruction sequencing in pipeline processors

G - Physics

06

F

342/21, 354/230.

G06F 9/26 (2006.01) G06F 9/28 (2006.01)

Patent

CA 1165453

ABSTRACT OF THE DISCLOSURE The microinstructions controlling a pipeline processor are held in a control store that is partitioned into two microcode memory banks. The invention can support three modes of sequencing; single microinstruction, sequen- tial multiple microinstructions, and multiple microinstructions with conditional branching. When a conditional branch is performed, the branch not taken path is assumed and if true, the microinstruction following the branch is executed with no delay. If the branch is taken, the guess is purged and following a one clock delay, the branched to microinstruction is executed. The invention supports these sequencing modes at the maximum pipeline rate, since the only logic between registers is the memory chips.

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