G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.71
G06F 9/22 (2006.01) G06F 9/308 (2006.01)
Patent
CA 1119307
MICROCOMPUTER HAVING SEPARATE BIT AND WORD ACCUMULATORS AND SEPARATE BIT AND WORD INSTRUCTION SETS Abstract of the Disclosure A microprocessor chip architecture provides separate bit and word arithmetic and logic unit (ALU) and ac- cumulator sets for processing data and executing in- structions on either a bit or word basis. Separate instruction sets are provided for bit and word pro- cessing. The single bit instruction set is executed by the single bit ALU-accumulator set for serial opera- tions and these instructions are designed to facilitate I/O operations. The word instruction set is executed by the word ALU-accumulator set for parallel operations and these instructions are designed to facilitate data transfer and manipulation. The address space includes a region which may be addressed on both a bit and word basis, thereby enabling the same data to be processed either as bits or words in order to optimize the current operation. Each bit of the word accumulator is ad- dressable by the bit instructions, thereby eliminating the need for mask operations. An example is described in the use of both bit and word processing facilities to execute a double frequency (F/2F) data separation operation. SA977062
337635
International Business Machines Corporation
Na
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