Microcomputer system employing address offset mechanism to...

Details Microcomputer system employing address offset mechanism to... Microcomputer system employing address offset mechanism to...

G - Physics

06

F

354/241

G06F 13/00 (2006.01) G06F 12/00 (2006.01) G06F 12/08 (2006.01) G06F 13/16 (2006.01)

Patent

CA 2016399

The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

Affiliated with

Also associated with

Rating

Microcomputer system employing address offset mechanism to... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microcomputer system employing address offset mechanism to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microcomputer system employing address offset mechanism to... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1559961