Microelectronic fabrication method minimizing threshold...

Details Microelectronic fabrication method minimizing threshold... Microelectronic fabrication method minimizing threshold...

H - Electricity

01

L

356/176

H01L 21/265 (2006.01) H01L 21/425 (2006.01) H01L 27/108 (2006.01) H01L 29/10 (2006.01)

Patent

CA 1132722

ABSTRACT A microelectronic fabrication process for minimizing the threshold voltage variation across the surface of a wafer of semiconductor material. The process precisely specifies the degenerate (or heavily doped) impurity profile distribution by using ion implantation so as to minimize the autodoping of adjacent gate regions immediately after the ion implantation step prior to gate oxidation, while maximizing the surface concentration of the dopant at the ultimate silicon surface to achieve appropriate surface sheet resistance and junction depth after all circuit fabrication steps have been completed.

346436

Affiliated with

Also associated with

Rating

Microelectronic fabrication method minimizing threshold... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microelectronic fabrication method minimizing threshold..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microelectronic fabrication method minimizing threshold... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-936826