H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/128
H01L 21/95 (1985.01)
Patent
CA 1200617
Abstract: The present invention relates to a process for fabricating a MOS integrated circuit structure at a predetermined portion of a substrate. The process includes the steps of forming a continuous silicon layer on the substrate, forming a continuous silicon oxide layer on the silicon layer covering at least the predetermined portion and forming a polycrystalline silicon layer on the oxide layer such that the silicon layer is insulated from the portion. A conducting layer is formed on the poly- crystalline silicon layer and a resist layer is formed over the conducting layer. The resist layer is etched to form a mask having a truncated pyramidal shape. The conducting layer and the polycrystalline silicon layer is milled using the resist layer as a mask in order to form a gate element having a shape corresponding to the truncated pyramidal shape of the resist layer mask. A dopant is implanted into the silicon layer using the gate element as a mask so that lighter and shallower degenerately doped areas are formed under the edges of the gate element.
469969
Kirby Eades Gale Baker
Rockwell International Corporation
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