Microelectronic shadow masking process for reducing...

H - Electricity – 01 – L

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

356/128

H01L 29/423 (2006.01) H01L 21/027 (2006.01) H01L 21/266 (2006.01) H01L 21/336 (2006.01) H01L 29/49 (2006.01) H01L 29/786 (2006.01)

Patent

CA 1194613

- 20 - Abstract A process for forming a doped region in a substrate which is in alignment with a circuit member by forming a masking member on a layer, the masking member defining the outline on the circuit member; and etching the layer employing the masking member as a mask to define the circuit member, the etching continuing such that the circuit member includes sloping side faces. Subsequently, a dopant species is implanted into the substrate so as to form the doped region, the dosage and energy of ions implanted being selected such that ions are partially blocked by the portion of the circuit member beneath the sloping side faces thereby providing a more lightly doped and more shallow distribution of implanted species region than in other regions.

407811

LandOfFree

Say what you really think

Search LandOfFree.com for Canadian inventors and patents. Rate them and share your experience with other people.

Rating

Microelectronic shadow masking process for reducing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microelectronic shadow masking process for reducing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microelectronic shadow masking process for reducing... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFCA-PAI-O-1245792

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.