Microinstruction addressing in high-speed cpu

Details Microinstruction addressing in high-speed cpu Microinstruction addressing in high-speed cpu

G - Physics

06

F

354/230.72

G06F 9/26 (2006.01) G06F 7/78 (2006.01) G06F 9/30 (2006.01)

Patent

CA 1323939

MICROINSTRUCTION ADDRESSING IN HIGH-SPEED CPU ABSTRACT A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An uncondi- tional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the micro- instruction does not prevent completion of the stack operation in one machine cycle.

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