G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.71
G06F 9/22 (2006.01) G06F 9/26 (2006.01) G06F 9/28 (2006.01)
Patent
CA 2030404
MICROINSTRUCTION SEQUENCER ABSTRACT OF THE DISCLOSURE First and second banks of control stores are used to store microinstructions. Each tank contains three control stores: A horizontal control store, a vertical control store, and a jump control store. The horizontal control store contains the rank four microcode; the vertical control store contains the rank three microcode; and the jump control store contains the same microcode as the vertical control store but is used on conditional jump microoperations. In one embodiment of the invention, the contents of the vertical control store are logically offset from their original address by 1 whereas the contents of the horizontal control store and the jump control store are aligned with their original address. In another embodiment, the contents of the horizontal control store and the jump control store are offset from their original addresses by one, whereas the contents of the vertical control store are aligned with their original addresses. This allows simultaneous accessing of different microinstructions using a single address counter. The control store banks are accessed in an overlapping manner so that upon each clock cycle one bank is loading the rank 3 and rank 4 registers. The contents of the two banks are the same to provide soft error coverage and recovery. The sequencer according to the present invention includes a return address stack for returning from subroutine calls and trap routines. When processing trap routines, the return address stack stores two microinstruction addresses to allow processing of a previously encountered jump or call operation that may have been aborted when the trap routine was entered.
Harris Richard
Horst Robert W.
Rahman Mizanur M.
Smart & Biggar
Tandem Computers Incorporated
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