Microprocessor architecture for improved chip testability

Details Microprocessor architecture for improved chip testability Microprocessor architecture for improved chip testability

G - Physics

06

F

354/225, 324/58.

G06F 11/00 (2006.01) G06F 11/267 (2006.01)

Patent

CA 1143069

SHOJI-7 MICROPROCESSOR ARCHITECTURE FOR IMPROVED CHIP TESTABILITY Abstract of the Disclosure An improved architecture for a single chip microprocessor CPU includes provision for directly observing at its terminals the control signals from its instruction decoder to facilitate functional testing of the chip. The CPU, upon receiving a command signal transfers the signals on the control lines (2091 409, 509) of its instruction decoder to its output terminals. In one embodiment of the invention the command signal is applied to the CPU chip at a designated input terminal. In another embodiment, the command signal is applied through a special instruction. The improvements permit increased functional test fault coverage and shorter test programs.

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