G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 15/167 (2006.01) G06F 12/08 (2006.01) G06F 13/20 (2006.01)
Patent
CA 2228061
A method is described of managing memory in a microprocessor system comprising two or more processors (40, 42). Each processor (40, 42) has a cache memory (44, 46) and the system has a system memory (48) divided into pages subdivided into blocks. The method is concerned with managing the system memory (48) identifying areas thereof as being "cacheable", "non-cacheable" or "free". Safeguards are provided to ensure that blocks of system memory (48) cannot be cached by two different processors (40, 42) simultaneously.
Méthode de gestion de la mémoire d'un microsystème constitué d'au moins deux processeurs (40, 42). Chaque processeur (40, 42) est doté d'une mémoire-cache (44, 46), et le système est doté d'une mémoire-système (48) divisée en pages elles-mêmes subdivisées en blocs. La méthode a trait à la gestion de la mémoire-système (48) par identification des zones pouvant être utilisées comme cache, des zones ne pouvant servir de cache et des zones libres. Des sauvegardes font en sorte que des blocs de la mémoire-système (48) ne peuvent servir de cache simultanément à deux processeurs (40, 42).
Bereskin & Parr
Ncipher Corporation Limited
LandOfFree
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