G - Physics – 06 – F
Patent
G - Physics
06
F
354/67, 354/230.
G06F 9/26 (2006.01) G06F 9/28 (2006.01) G06F 9/38 (2006.01)
Patent
CA 1324447
ABSTRACT OF THE DISCLOSURE A central processing unit (CPU) 10 comprises an external control memory for storing microinstructions which correspond to macroinstructions read from a system memory. The microinstructions are 56 bits in length and are read in 28-bit segments. CPU 10 also comprises an internal memory management unit (MMU) 18 which comprises a plurality of address translation entry (ATE) registers four of which are permanent and sixteen of which are temporary in that the storage of a new translation entry occurs in a least recently used temporary translation entry register. CPU 10 also comprises a plurality of status register bits, some of which are settable only by predefined microinstructions. All of the status register bits are branchable. CPU 10 further comprises a condition code register the state of which may be determined by input signal pins. CPU 10 also comprises address generation logic which may generate a 24, 31 or 32 bit address upon a 32-bit address bus. The address generation logic is further operable for generating a memory storage address; the data being supplied by external logic, such as a coprocessor.
598463
Bessolo Jeffrey M.
Lang Steven E.
Lee Raymond Y.
Nathan Jeffrey D.
Shah Vyomesh
Lg Semicon Co. Ltd.
Smart & Biggar
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